Thursday, October 4, 2012

EI2253 DIGITAL LOGIC CIRCUITS SYLLABUS | ANNA UNIVERSITY BE E&I 4TH SEM SYLLABUS REGULATION 2008 2011 2012-2013

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EI2253 DIGITAL LOGIC CIRCUITS SYLLABUS | ANNA UNIVERSITY BE E&I 4TH SEM SYLLABUS REGULATION 2008 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY FOURTH SEMESTER BE ELECTRONICS AND INSTRUMENTATION ENGINEERING DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,PREVIOUS YEAR QUESTION PAPERS,MODEL QUESTION PAPERS, CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009

EI2253 DIGITAL LOGIC CIRCUITS LT P C
3 1 0 4
AIM
To introduce the fundamentals of digital circuits, combinational and sequential circuit.
OBJECTIVES
i. To study various number systems and to simplify the mathematical expressions using
Boolean functions – simple problems.
ii. To study implementation of combinational circuits
iii. To study the design of various synchronous and asynchronous circuits.
iv. To expose the students to various memory devices.
UNIT I NUMBER SYSTEMS AND BOOLEAN ALGEBRA 9
Review of number systems; types and conversion, codes. Boolean algebra: De-Morgan’s theorem,
switching functions and simplification using K-maps and Quine McCluskey method.
UNIT II COMBINATIONAL CIRCUITS 9
Design of Logic gates. Design of adder, subtractor, comparators, code converters, encoders,
decoders, multiplexers and demultiplexers. Function realization using gates and multiplexers.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 9
Flip flops - SR, D, JK and T. Analysis of synchronous sequential circuits; design of synchronous
sequential circuits – Completely and incompletely specified sequential circuits - state diagram; state
reduction; state assignment, Counters – synchronous, a synchronous, updown and Johnson
counters; shiftregisters.
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UNIT IV ASYNCHRONOUS SEQUENCTIAL CIRCUITS 9
Analysis of asynchronous sequential machines, state assignment, asynchronous Design problem.
UNIT V MEMORY DEVICES, PROGRAMMABLE LOGIC DEVICES AND LOGIC
FAMILIES 9
Memories: ROM, PROM, EPROM, PLA, PLD, FPGA, digital logic families: TTL, ECL, CMOS.
L = 45 T = 15 TOTAL = 60 PERIODS
TEXT BOOKS:
1. M. Morris Mano, ‘Digital Logic and Computer Design’, Prentice Hall of India, 2002.
2. John M.Yarbrough, ‘Digital Logic, Application & Design’, Thomson, 2002.
REFERENCES:
1. Charles H.Roth, ‘Fundamentals Logic Design’, Jaico Publishing, IV edition, 2002.
2. Floyd, ‘Digital Fundamentals’, 8th edition, Pearson Education, 2003.
3. John F.Wakerly, ‘Digital Design Principles and Practice’, 3rd edition, Pearson
Education, 2002.