Trending: Anna University 8th Sem Results April 2014 May/June 2014 Time Table/ Internal Marks Calculate CGPA Online SSLC Results 2014 12th Result 2014

Test Footer 1

Friday, January 10, 2014

CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN Syllabus | Anna University Regulation 2013 BE/B Tech First Year Second Semester Syllabus

Latest: TNEA 2014 Engineering Application Status, Counselling Date, Rank List
CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN Syllabus | Anna University Regulation 2013 BE/B Tech First Year Second Semester Syllabus. Below is the Anna University 2013 Regulation Syllabus for 2nd Semester for CSE Computer Science Engineering, Textbooks, Reference books, Exam portions, Question Bank, Previous year question papers, Model question papers, Class notes, Important 2 marks, 8 marks, 16 marks topics. It is applicable for all students admitted in the Academic year 2013-2014 onwards for all its Affiliated institutions in Tamil nadu.


CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C 3 0 0 3

OBJECTIVES:
 Learn how to design digital circuits, by simplifying the Boolean functions. Also, gives an idea
about designs using PLDs, and writing codes for designing larger digital systems.
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9
Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and
Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map and
Tabulation Methods – Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 9
Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic Operations, Code
Conversion – Decoders and Encoders – Multiplexers and Demultiplexers – Introduction to HDL –
HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 9
Sequential Circuits – Latches and Flip Flops – Analysis and Design Procedures – State Reduction
and State Assignment – Shift Registers – Counters – HDL for Sequential Logic Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 9
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables –
Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 9
RAM and ROM – Memory Decoding – Error Detection and Correction – Programmable Logic Array –
Programmable Array Logic – Sequential Programmable Devices – Application Specific Integrated
Circuits.
TOTAL: 45 PERIODS
8
TEXT BOOK:
1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008.
REFERENCES:
1. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education,
2007.
2. Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House,
Mumbai, 2003.
3. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003.

4. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010.

No comments:

Post a Comment

Any doubt ??? Just throw it Here...