## Monday, July 16, 2012

### CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN SYLLABUS | ANNA UNIVERSITY BTECH IT 3RD SEMESTER SYLLABUS REGULATION 2008 2011-2012

Latest: Anna University May/June 2014 Time Table revised Exam Date 7-4-2014

CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN SYLLABUS | ANNA UNIVERSITY BTECH IT 3RD SEMESTER SYLLABUS REGULATION 2008 2011-2012 BELOW IS THE ANNA UNIVERSITY THIRD SEMESTER BTECH INFORMATION TECHNOLOGY DEPARTMENT SYLLABUS IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011-2012 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009

CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C
(Common to CSE & IT) 3 1 0 4
AIM
To provide an in-depth knowledge of the design of digital circuits and the use of
Hardware Description Language in digital system design.
OBJECTIVES
 To understand different methods used for the simplification of Boolean functions
 To design and implement combinational circuits
 To design and implement synchronous sequential circuits
 To design and implement asynchronous sequential circuits
 To study the fundamentals of VHDL / Verilog HDL
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 8
Review of binary number systems - Binary arithmetic – Binary codes – Boolean algebra
and theorems - Boolean functions – Simplifications of Boolean functions using
Karnaugh map and tabulation methods – Logic gates
UNIT II COMBINATIONAL LOGIC 9
Combinational circuits – Analysis and design procedures - Circuits for arithmetic
operations - Code conversion – Introduction to Hardware Description Language (HDL)
UNIT III DESIGN WITH MSI DEVICES 8
Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable
logic - HDL for combinational circuits
UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC 10
Sequential circuits – Flip flops – Analysis and design procedures - State reduction and
state assignment - Shift registers – Counters – HDL for Sequential Circuits.
UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC 10
Analysis and design of asynchronous sequential circuits - Reduction of state and flow
tables – Race-free state assignment – Hazards. ASM Chart
TUTORIAL: 15 TOTAL : 60PERIODS
TEXT BOOK
1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2007.
REFERENCES:
1. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico Publishing
House, Latest Edition.
2. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2007.