## Monday, May 21, 2012

### EC2203 DIGITAL ELECTRONICS SYLLABUS | ANNA UNIVERSITY ECE THIRD SEMESTER SYLLABUS REGULATION 2008 2011-2012

Latest: TNEA 2014 Engineering Application Status, Counselling Date, Rank List

EC2203 DIGITAL ELECTRONICS SYLLABUS | ANNA UNIVERSITY ECE THIRD SEMESTER SYLLABUS REGULATION 2008 2011-2012
EC2203 DIGITAL ELECTRONICS QUESTION BANK/MODEL QUESTION PAPER 1 FOR NOV/DEC EXAM CLICK HERE

EC2203 DIGITAL ELECTRONICS QUESTION BANK/MODEL QUESTION PAPER 2 FOR NOV/DEC EXAM CLICK HERE

BELOW IS THE ANNA UNIVERSITY 3RD SEMESTER BE ELECTRONICS AND COMMUNICATION DEPARTMENT SYLLABUS IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011-2012(ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009.
EC 2203 DIGITAL ELECTRONICS L T P C
3 1 0 4
AIM
To learn the basic methods for the design of digital circuits and provide the fundamental
concepts used in the design of digital systems.
OBJECTIVES
 To introduce basic postulates of Boolean algebra and shows the correlation between
Boolean expressions
 To introduce the methods for simplifying Boolean expressions
 To outline the formal procedures for the analysis and design of combinational circuits
 and sequential circuits
 To introduce the concept of memories and programmable logic devices.
 To illustrate the concept of synchronous and asynchronous sequential circuits
UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 12
Minimization Techniques: Boolean postulates and laws – De-Morgan’s Theorem -
Principle of Duality - Boolean expression - Minimization of Boolean expressions ––
Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map
Minimization – Don’t care conditions - Quine-McCluskey method of minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NORImplementations
of Logic Functions using gates, NAND–NOR implementations – Multi
level gate implementations- Multi output gate implementations. TTL and CMOS Logic
and their characteristics – Tristate gates
UNIT II COMBINATIONAL CIRCUITS 12
Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor - Parallel
Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/
Demultiplexer – decoder - encoder – parity checker – parity generators - code
converters - Magnitude Comparator.
UNIT III SEQUENTIAL CIRCUITS 12
Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation
–Application table – Edge triggering – Level Triggering – Realization of one flip flop
using other flip flops – serial adder/subtractor- Asynchronous Ripple or serial counter –
Asynchronous Up/Down counter - Synchronous counters – Synchronous Up/Down
counters – Programmable counters – Design of Synchronous counters: state diagram-
State table –State minimization –State assignment - Excitation table and maps-Circuit
implementation - Modulo–n counter, Registers – shift registers - Universal shift registers
– Shift register counters – Ring counter – Shift counters - Sequence generators.
UNIT IV MEMORY DEVICES 12
Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM –
EAPROM, RAM – RAM organization – Write operation – Read operation – Memory
cycle - Timing wave forms – Memory decoding – memory expansion – Static RAM Cell-
Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic
Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Field
Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits
using ROM, PLA, PAL
27
UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS 12
Synchronous Sequential Circuits: General Model – Classification – Design – Use of
Algorithmic State Machine – Analysis of Synchronous Sequential Circuits
Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode
circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits –
Design of Hazard Free Switching circuits. Design of Combinational and Sequential
circuits using VERILOG
TUTORIAL =15, TOTAL : 60 PERIODS
TEXT BOOKS
1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 /
Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.
2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas
Publishing House Pvt. Ltd, New Delhi, 2006
REFERENCES
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.
3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th
Edition, TMH, 2003.
5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.
6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New
Delhi, 2003
7. Donald D.Givone, Digital Principles and Design, TMH, 2003.