## Wednesday, September 12, 2012

### EE2255 DIGITAL LOGIC CIRCUITS SYLLABUS | ANNA UNIVERSITY BE EEE ENGINEERING 4TH SEM SYLLABUS REGULATION 2008 2011 2012-2013

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EE2255 DIGITAL LOGIC CIRCUITS SYLLABUS | ANNA UNIVERSITY BE EEE ENGINEERING 4TH SEM SYLLABUS REGULATION 2008 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY FOURTH SEMESTER BE ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009

EE2255 DIGITAL LOGIC CIRCUITS L T P C
3 1 0 4
AIM
To introduce the fundamentals of Digital Circuits, combinational and sequential circuit.
OBJECTIVES
i. To study various number systems and to simplify the mathematical expressions
using Boolean functions – simple problems.
ii. To study implementation of combinational circuits
iii. To study the design of various synchronous and asynchronous circuits.
iv. To expose the students to various memory devices.
v. To introduce digital simulation techniques for development of application oriented logic
circuit.
UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 9
Boolean algebra: De-Morgan’s theorem, switching functions and simplification using K-maps &
Quine McCluskey method, Design of adder, subtractor, comparators, code converters, encoders,
decoders, multiplexers and demultiplexers.
UNIT II SYNCHRONOUS SEQUENTIAL CIRCUITS 9
Flip flops - SR, D, JK and T. Analysis of synchronous sequential circuits; design of synchronous
sequential circuits – Counters, state diagram; state reduction; state assignment.
42
UNIT III ASYNCHRONOUS SEQUENCTIAL CIRCUIT 9
Analysis of asynchronous sequential machines, state assignment, asynchronous design problem.
UNIT IV PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES 9
Memories: ROM, PROM, EPROM, PLA, PLD, FPGA, digital logic families: TTL, ECL, CMOS.
UNIT V VHDL 9
RTL Design – combinational logic – Types – Operators – Packages – Sequential circuit – Sub
programs – Test benches. (Examples: adders, counters, flipflops, FSM, Multiplexers /
Demultiplexers).
L = 45 T = 15 TOTAL: 60 PERIODS
TEXT BOOKS
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition, 2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006.
3. John M.Yarbrough, ‘Digital Logic, Application & Design’, Thomson, 2002.
REFERENCES
1. Charles H.Roth, ‘Fundamentals Logic Design’, Jaico Publishing, IV edition, 2002.
2. Floyd and Jain, ‘Digital Fundamentals’, 8th edition, Pearson Education, 2003.
3. John F.Wakerly, ‘Digital Design Principles and Practice’, 3rd edition, Pearson
Education, 2002.
4. Tocci, “Digital Systems : Principles and applications, 8th Edition” Pearson Education.