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EC2354 VLSI DESIGN SYLLABUS | ANNA UNIVERSITY BE ECE ENGINEERING 6TH SEM SYLLABUS REGULATION 2008 2011 2012-2013

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EC2354 VLSI DESIGN SYLLABUS | ANNA UNIVERSITY BE ECE ENGINEERING 6TH SEM SYLLABUS REGULATION 2008 2011 2012-2013 BELOW IS THE ANNA UNIVERSITY SIXTH SEMESTER BE  ELECTRONICS AND COMMUNICATION ENGINEERING  DEPARTMENT SYLLABUS, TEXTBOOKS, REFERENCE BOOKS,EXAM PORTIONS,QUESTION BANK,CLASS NOTES, IMPORTANT 2 MARKS, 8 MARKS, 16 MARKS TOPICS. IT IS APPLICABLE FOR ALL STUDENTS ADMITTED IN THE YEAR 2011 2012-2013 (ANNA UNIVERSITY CHENNAI,TRICHY,MADURAI,TIRUNELVELI,COIMBATORE), 2008 REGULATION OF ANNA UNIVERSITY CHENNAI AND STUDENTS ADMITTED IN ANNA UNIVERSITY CHENNAI DURING 2009


EC2354 VLSI DESIGN L T P C
3 0 0 3
AIM
To introduce the technology, design concepts and testing of Very Large Scale Integrated
Circuits.
OBJECTIVES
 To learn the basic CMOS circuits.
 To learn the CMOS process technology.
 To learn techniques of chip design using programmable devices.
 To learn the concepts of designing VLSI subsystems.
 To learn the concepts of modeling a digital system using Hardware Description
Language.
UNIT I CMOS TECHNOLOGY 9
A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal IV
effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS
process enhancements, Technology related CAD issues, Manufacturing issues
UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION 9
Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect,
Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device
characterization, Circuit characterization, Interconnect simulation
UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9
Circuit families –Low power logic design – comparison of circuit families – Sequencing
static circuits, circuit design of latches and flip flops, Static sequencing element
methodology- sequencing dynamic circuits – synchronizers
UNIT IV CMOS TESTING 9
Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon
debug principles- Manufacturing test – Design for testability – Boundary scan
UNIT V SPECIFICATION USING VERILOG HDL 9
Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls,
procedural assignments conditional statements, Data flow and RTL, structural gate level
switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches,
Structural gate level description of decoder, equality detector, comparator, priority
encoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.
TOTAL = 45 PERIODS
TEXT BOOKS
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005
2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.
REFERENCES
1. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003
2. Wayne Wolf, Modern VLSI design, Pearson Education, 2003
3. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997
4. J.Bhasker: Verilog HDL primer, BS publication,2001
5. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003

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